1. Field of the Invention
This invention relates generally to apparatus associated with an integrated circuit memory array and, more particularly, to the detectors of address signals, typically referred to as address transition detectors. The address transition detectors facilitate the random access of integrated circuit memory locations.
2. Description of the Related Art
Address transition detectors are typically used in semiconductor memory products to speed up the random access of data. By internally precharging and equalizing heavily capacitively loaded data input/output lines (i.e., lines which are internal to the integrated circuit chip) whenever new data is to be retrieved from the memory array, the time required to retrieve the data is reduced. In most memory systems, the procedure for withdrawing data from the memory array begins with the application of new memory array address signals on the system address bus. The memory device, in response to the application of these signals, internally decodes the address of the requested data and applies the correct information signals on the data bus some period of time after the address has been decoded. It will be clear that the an address signal (transition) is present on at least one of the address lines if new information is requested.
Several problems arise in the design and use of address transition detectors (ATD) to identify the presence of an address signal on the system bus. The speed with which the address transition detectors detect an address transition and generate a usable signal internally is one the important components in the effort to reduce the access time for retrieval of information from the memory device. In addition, the ability of the address transition detector to respond properly to spurious address line noise is a problem that must be considered in the design of the these devices.
The ideal response of the address transition detector unit to a noise transient less than the internal address signal pulse width is shown in FIG. 1. A very small pulse applied to the input of the address transition detector provides an output signal from the address transition detector which is of the form required by the internal summing circuit. (The internal summing circuit referred to here takes the results of multiple address transition detectors and sums them together to provide a single signal pulse in the event of the detection of one or more address transitions.) As the input address signal pulse increases in width, i.e., the interval between the leading edge 11 of the input pulse and the trailing edge 12-15 increases, the interval between the leading edge 10' and the trailing edges 11'-15' of the output pulse from the address transition detector unit similarly increases. A constant time delay is provided between the trailing edge of the input address pulse and the trailing edge of the output signal of the address transition detector unit.
In the past, a number of circuit implementations have been used for the address transition detector. However, most have failed to exhibit the desired response to very narrow noise transients. The failure of these implementations is due to the number of buffer stages between the internal address signal and the output of the address transition detector. The more stages of inverting amplifiers or gates in the signal path, the wider the disturbing transient must be before the address transition detector unit can respond properly. Other approaches have failed to exhibit the desired relationship between the trailing edge of the address signal and the trailing edge of the output signal from the address transition detection. This failure has led to improper circuit operation due to internal timing skews between the arrival of the data at the input of amplifiers in the data path and the activation of those amplifiers.
A need has therefore been felt for an address transition detection which can provide a constant detail between the trailing edge of an address signal and the output signal from an address transition detector unit. In addition, the address transition detector unit should be responsive to narrow pulses which are applied thereto.